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[ak5388] ms1096-e-01 2009/08 - 1 - general description the ak5388 is a 24bit, 216khz samp ling 4-channel a/d converter fo r high-end audio systems. the modulator in the ak5388 uses akm ?s enhanced dual bit architectu re, enabling the ak5388 to realize high accuracy and low cost. the ak5388 achiev es 120db dynamic range and 110db s/(n+d), and an optional mono mode extends dynamic range to 123db. the ak5388?s digita l filter features a modified fir architecture that minimizes group delay while mainta ining excellent linear phase response. so the device is suitable for professional audi o applications including recordi ng, sound reinforcement, effects processing, sound cards, and high-end a/v receivers. the ak5388 is available in 44pin lqfp package. features ? sampling rate: 8khz ~ 216khz ? full differential inputs ? s/(n+d): 110db ? dr, s/n: 120db(mono mode: 123db) ? short delay digital filter (gd=12.6/fs) ? passband: 0~21.648khz (@fs=48khz) ? ripple: 0.01db ? stopband: 80db ? digital hpf ? power supply: 4.75 ~ 5.25v(a nalog), 3.0 ~ 3.6v(digital) ? output format: 24bit msb justified, i 2 s or tdm ? cascade tdm i/f: 8ch/48khz, 4ch/96khz, 4ch/192khz ? master & slave mode ? overflow flag ? power dissipation: 575 mw (@fs=48khz) ? package: 44pin lqfp ? modulator lin1- lrck bick sdto1 vcom1 clock divider avd d2 avdd1 decimation filter audio interface voltage reference dvdd1 vss6 pdn lin1+ ? modulator rin1- decimation filter rin1+ ? modulator lin2- decimation filter lin2+ ? modulator rin2- decimation filter rin2+ sdto2 dif tdm0 msn mclk tdmin tdm1 dvdd2 ovf vcom2 vss1 vss3 vss4 vss5 hpf mono cks0 cks2 vrefl1 vrefp2 vrefl2 vrefp1 cks2 ak5388 120db 24-bit 192khz 4-channel adc
[ak5388] ms1096-e-01 2009/08 - 2 - ordering guide AK5388EQ ?10 ~ +70 c 44pin lqfp (0.8mm pitch) akd5388 evaluation board for ak5388 pin layout vrefp2 rin2+ 34 vrefl2 3 3 35 vc om 2 36 lin2+ 37 lin2- 38 test3 39 r in1- 40 rin1+ 41 vc om 1 42 vrefl1 43 vrefp1 44 rin2- 32 vss6 31 a vdd2 30 test2 29 vss5 28 vss4 2 7 dvdd2 2 6 hpfe 25 mono 24 dif 23 lin1+ 1 lin1- 2 vss1 3 avdd1 4 test1 5 vss2 6 cks 0 7 cks1 8 cks 2 9 pdn 10 m/sn 11 22 21 20 19 18 17 16 15 14 13 12 tdm1 tdm0 tdmin ovf sdto2 sdto1 vss3 dvdd1 lrck bick mclk AK5388EQ top view
[ak5388] ms1096-e-01 2009/08 - 3 - pin / function no. pin name i/o function 1 lin1+ i adc1 lch positive analog input pin 2 lin1 ? i adc1 lch negative analog input pin 3 vss1 - ground pin 4 avdd1 - analog power supply pin, 4.75 5.25v 5 test1 i test pin (connected to vss1-6) 6 vss2 ground pin 7 cks0 i clock mode select #0 pin 8 cks1 i clock mode select #1 pin 9 cks2 i clock mode select #2 pin 10 pdn i power-down mode pin when ?l?, the circuit is in power-down mode. the ak5388should always be reset upon power-up. 11 msn i master/slave mode select pin ?l?: slave mode, ?h?: master mode 12 mclk i master clock input pin 13 bick i/o audio serial data clock pin ?l? output in master mode at power-down mode. 14 lrck i/o output channel clock pin ?l? output in master mode at power-down mode. 15 dvdd1 - digital power supply pin, 3.0 3.6v 16 vss3 - ground pin 17 sdto1 o adc1 audio serial data output pin ?l? output at power-down mode. 18 sdto2 o adc2 audio serial data output pin ?l? output at power-down mode. 19 ovf o analog input overflow detect pin this pin goes to ?h? if any analog inputs overflows. ?l? output at power-down mode. 20 tdmin i tdm data input pin 21 tdm0 i tdm i/f format enable pin ?l? : normal mode, ?h? : tdm mode 22 tdm1 i tdm i/f bick frequency select pin ?l? : normal mode, ?h? : tdm mode 23 dif i audio interface format pin ?l?: 24bitmsb justified, ?h?: 24biti 2 s compatible 24 mono i stereo/mono mode select pin ?l?: stereo mode, ?h?: mono mode 25 hpfe i hpf enable pin ?l?: disable, ?h? enable 26 dvdd2 - digital power supply pin, 3.0 3.6v 27 vss4 - ground pin 28 vss5 ground pin
[ak5388] ms1096-e-01 2009/08 - 4 - no. pin name i/o function 29 test2 i test pin (connected to vss1-6) 30 avdd2 - analog power supply pin, 4.75 5.25v 31 vss6 - ground pin 32 rin2 ? i adc2 rch negative analog input pin 33 rin2+ i adc2 rch positive analog input pin 34 vrefp2 i adc2 high level voltage reference input pin 35 vrefl2 i adc2 low level voltage reference input pin 36 vcom2 o common voltage output pin, (avdd2)/2 normally connected to avss2 with a 0.1 f ceramic capacitor in parallel with an electrolytic capacitor less than 2.2 f. 37 lin2+ i adc2 lch positive analog input pin 38 lin2 ? i adc2 lch negative analog input pin 39 test3 i test pin (connected to vss1-6) 40 rin1 ? i adc1 rch negative analog input pin 41 rin1+ i adc1 rch positive analog input pin 42 vcom1 o common voltage output pin, (avdd1)/2 normally connected to avss1 with a 0.1 f ceramic capacitor in parallel with an electrolytic capacitor less than 2.2 f. 43 vrefl1 i adc1 low level voltage reference input pin 44 vrefp1 i adc1 high level voltage reference input pin note: all digital input pins should not be left floating.
[ak5388] ms1096-e-01 2009/08 - 5 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting lin1+/ ? , rin1+/ ? these pins should be connected to vss1-6 analog lin2+/ ? , rin+/ ? these pins should be connected to vss1-6 ovf this pin should be open. test1 this pin should be connected to vss1-6 test2 this pin should be connected to vss1-6 digital test3 this pin should be connected to vss1-6 absolute maximum ratings (vss1-6=0v; note 1 ) parameter symbol min max units power supplies: analog analog digital digital output buffer avdd1 avdd2 dvdd1 dvdd2 ? 0.3 ? 0.3 ? 0.3 ? 0.3 6.0 6.0 6.0 6.0 v v v v input current, any pin except supplies iin ? 10 ma analog input voltage ( note 2 ) vina vina ? 0.3 ? 0.3 avdd1+0.3 avdd2+0.3 v digital input voltage ( note 3 ) vind vind ? 0.3 ? 0.3 dvdd1+0.3 dvdd2+0.3 v ambient temperature (power applied) ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to vss1-6 pins. note 2. vrefp1, vrefp2, vrefl1, vrefl2, ainl 1/2+, ainl1/2-, ainr1/2+ and ainr1/2- pins note 3. pdn, cks0, cks1, cks2, tdmin, mclk, bick , lrck, dif, tdm0, tdm1, hpfe, mono and tst1/2/3 pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ak5388] ms1096-e-01 2009/08 - 6 - recommended operating conditions (vss1-6=0v; note 1 ) parameter symbol min typ max units power supplies: analog analog avdd1 avdd2 4.75 4.75 5.0 5.0 5.25 5.25 v v ( note 4 ) digital dvdd1/2 3.0 3.3 3.6 v voltage reference ( note 5 ) ?h? voltage reference ?l? voltage reference vrefp1 ? vrefl1 vrefp2 ? vrefl2 vrefp1 vrefp2 vrefl1 vrefl2 vref vref avdd1-0.5 avdd2-0.5 vss1-6 vss1-6 avdd1-0.5 avdd2-0.5 - - - - - - avdd1 avdd2 - - avdd1 avdd2 v v v v v v note 1. all voltages with respect to vss1-6 pins. note 4. the power up sequence between avdd1/2 and dvdd1/2 is not critical. note 5. vrefl? and vrefr? pins should be connected to vss1-6 pins. analog input voltage scales with voltage of {(vrefp) ? (vrefl)}. vin (typ, @ 0db) = 2.8 x {(vref+) ? (vref?)} / 5 [v]. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
[ak5388] ms1096-e-01 2009/08 - 7 - analog characteristics (ta = 25 c; avdd1/2=5.0v; dvdd1/2=3.3v; vss1-6=0v; vrefp1=vrefp2=avdd, vrefl1 = vrefl2 = vss1-6; fs=48khz, 96khz, 192khz; bick=64fs; signal fr equency=1khz; 24bit data; measurement frequency=10hz 20khz at fs = 48khz, 40hz 40khz at fs = 96khz, 40hz 40khz at fs = 192khz; unless otherwise specified) parameter min typ max units analog input characteristics: resolution - - 24 bits input voltage ( note 6 ) 2.7 2.8 2.9 vpp fs=48khz bw=20khz ? 1dbfs ? 20dbfs ? 60dbfs 100 - - 110 97 57 - - - db db db fs=96khz bw=40khz ? 1dbfs ? 20dbfs ? 60dbfs 97 - - 107 90 50 - - - db db db s/(n+d) fs=192khz bw=40khz ? 1dbfs ? 20dbfs ? 60dbfs - - - 107 90 50 - - - db db db dynamic range ( ? 60dbfs with a-weighted) stereo mode mono mode 114 - 120 123 - - db s/n (a-weighted) stereo mode mono mode 114 - 120 123 - - db input resistance 3.3 3.7 4.1 k interchannel isolation 110 120 db interchannel gain mismatch 0.1 0.5 db power supply rejection ( note 7 ) 60 - db power supplies power supply current normal operation (pdn pin = ?h?) avdd1/2 dvdd (fs=48khz) dvdd (fs=96khz) dvdd (fs=192khz) power down mode (pdn pin = ?l?) ( note 8 ) avdd+dvdd 105 15 27 20 10 130 22 39 29 100 ma ma ma ma a note 6. this value is (lin+) ? (lin ? ) and (rin+) ? (rin ? ). input voltage is proportional to vref voltage. vin = 0.56 x vref1/2 (vpp). note 7. psr is applied to avdd1/2 and dvdd1/2 with 1khz, 20mvpp. the vrefp1 and vre fp2 pins held a constant voltage. note 8. all digital input pins are held dvdd1/2 or vss3/4.
[ak5388] ms1096-e-01 2009/08 - 8 - filter characteristics (fs=48khz) (ta=25 c; avdd1/2=4.75 5.25v; dvdd1/2=3.0 3.6v; dfs1 = ?l?, dfs0 = ?l?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 9 ) ? 0.01db ? 0.1db ? 3.0db ? 6.0db pb 0 - - - 22.0 23.8 24.4 21.6 - - - khz khz khz khz stopband sb 27.9 khz passband ripple pr 0.01 db stopband attenuation sa 80 db group delay ( note 10 ) gd 12.6 1/fs group delay distortion gd 0.01 s adc digital filter (hpf): frequency response ( note 9 ) ? 3db ? 0.1db fr 1.0 6.5 hz hz filter characteristics (fs=96khz) (ta=25 c; avdd1/2=4.75 5.25v; dvdd1/2=3.0 3.6v; dfs1 = ?l?, dfs0 = ?h?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 9 ) ? 0.01db ? 0.1db ? 3.0db ? 6.0db pb 0 - - - 44.2 47.6 48.9 43.3 - - - khz khz khz khz stopband sb 55.9 khz passband ripple pr 0.01 db stopband attenuation sa 80 db group delay ( note 10 ) gd 12.6 1/fs group delay distortion gd 0.013 s adc digital filter (hpf): frequency response ( note 9 ) ? 3db ? 0.1db fr 1.0 6.5 hz hz note 9. the passband and stopband frequencies scale with fs . the reference frequency of these responses is 1khz. note 10. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc.
[ak5388] ms1096-e-01 2009/08 - 9 - filter characteristics (fs=192khz) (ta=25 c; avdd1/2=4.75 5.25v; dvdd1/2=3.0 3.6v; dfs1 = ?h?, dfs0 = ?l?) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 11 ) ? 0.08db ? 0.1db ? 3.0db ? 6.0db pb - - - - - 83.4 99.9 106.5 83.0 - - - khz khz khz khz stopband sb 141.1 khz passband ripple pr 0.08 db stopband attenuation sa 80 db group delay ( note 12 ) gd 9.8 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 11 ) ? 3db ? 0.1db fr 1.0 6.5 hz hz note 11. the passband and stopband frequencies scale with fs . the reference frequency of these responses is 1khz. note 12. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. dc characteristics (ta=25 c; avdd1/2=4.75 5.25v; dvdd1/2=3.0 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd1 70%dvdd2 - - - - - - 30%dvdd1 30%dvdd2 v v v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol dvdd1 ? 0.4 dvdd2 ? 0.4 - - - - - 0.4 v v v input leakage current iin - - 10 a
[ak5388] ms1096-e-01 2009/08 - 10 - switching characteristics (ta=25 c; avdd1/2=4.75 5.25v; dvdd1/2=3.0 3.6v; c l =20pf) parameter symbol min typ max units master clock timing master clock 128fs: pulse width low pulse width high 192fs: pulse width low pulse width high 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high 768fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 1.024 0.4fclk 0.4fclk 1.536 0.4fclk 0.4fclk 2.048 0.4fclk 0.4fclk 3.072 0.4fclk 0.4fclk 4.096 0.4fclk 0.4fclk 6.144 0.4fclk 0.4fclk 24.576 36.864 12.288 18.432 24.576 36.864 27.648 41.472 27.648 41.472 27.648 41.472 mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrck timing (slave mode) normal mode (tdm1=?l?, tdm0=?l?) lrck frequency duty cycle fs duty 8 45 216 55 khz % tdm256 mode (tdm1=?l?, tdm0=?h?) lrck frequency ?h? time ?l? time fs tlrh tlrl 8 1/256fs 1/256fs 54 khz ns ns tdm128 mode (tdm1=?h?, tdm0=?h?) lrck frequency ?h? time ?l? time fs tlrh tlrl 8 1/128fs 1/128fs 216 khz ns ns lrck timing (master mode) normal mode (tdm1=?l?, tdm0=?l?) lrck frequency duty cycle fs duty 8 50 216 khz % tdm256 mode (tdm1=?l?, tdm0=?h?) lrck frequency ?h? time ( note 13 ) fs tlrh 8 1/8fs 54 khz ns tdm128 mode (tdm1=?h?, tdm0=?h?) lrck frequency ?h? time ( note 13 ) fs tlrh 8 1/4fs 216 khz ns note 13. ?l? time at i 2 s format
[ak5388] ms1096-e-01 2009/08 - 11 - parameter symbol min typ max units audio interface timing (slave mode) normal mode (tdm1=?l?, tdm0=?l?) bick period normal speed mode double , quad speed mode duty cycle lrck edge to bick ? ? ( note 14 ) bick ? ? to lrck edge ( note 14 ) lrck to sdto1/2 (msb) (except i 2 s mode) bick ? ? to sdto1/2 tbck tbck duty tlrb tblr tlrs tbsd 1/128fs 1/64fs 40 20 20 60 20 ns ns % ns ns ns ns tdm256 mode (tdm1=?l?, tdm0=?h?) bick period duty cycle lrck edge to bick ? ? ( note 14 ) bick ? ? to lrck edge ( note 14 ) bick ? ? to sdto1/2 ( note 15 ) tdmin setup time tbck duty tlrb tblr tbsd ttdms 1/256fs 40 20 20 16 60 20 ns % ns ns ns ns tdm128 mode (tdm1=?h?, tdm0=?h?) (8khz fs < 108khz) bick period duty cycle lrck edge to bick ? ? ( note 14 ) bick ? ? to lrck edge ( note 14 ) bick ? ? to sdto1 ( note 15 ) tbck duty tlrb tblr tbsd 1/128fs 40 20 20 60 20 ns % ns ns ns tdm128 mode (tdm1=?h?, tdm0=?h?) (108khz < fs 216khz) bick period duty cycle lrck edge to bick ? ? ( note 14 ) bick ? ? to lrck edge ( note 14 ) sdto1 setup time bick ? ? ( note 15 ) sdto1 hold time bick ? ? ( note 15 ) tbck duty tlrb tblr tbss tbsh 1/128fs 40 10 10 10 5 60 ns % ns ns ns ns
[ak5388] ms1096-e-01 2009/08 - 12 - parameter symbol min typ max units audio interface timing (master mode) normal mode (tdm1=?l?, tdm0=?l?) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto1/2 fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 20 hz % ns ns tdm256 mode (tdm1=?l?, tdm0=?h?) bick frequency bick duty ( note 16 ) bick ? ? to lrck bick ? ? to sdto1 ( note 15 ) fbck dbck tmblr tbsd ? 12 ? 20 256fs 50 12 20 hz % ns ns tdm128 mode (tdm1=?h?, tdm0=?h?) (8khz fs < 108khz) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto1 ( note 15 ) fbck dbck tmblr tbsd ? 12 ? 20 128fs 50 12 20 hz % ns ns tdm128 mode (tdm1=?h?, tdm0=?h?) (108khz < fs 216khz) bick frequency bick duty bick ? ? to lrck bick ? ? to sdto1 fbck dbck tmblr tbsd ? 6 ? 10 128fs 50 6 10 hz % ns ns power-down & reset timing pdn pulse width ( note 17 ) pdn ? ? to sdto1/2 valid ( note 18 ) tpd tpdv 150 516 ns 1/fs note 14. bick rising edge must not occur at the same time as lrck edge. note 15. sdto2 output is fixed to ?l?. note 16. this value is mclk=512fs. duty cycle is not guaranteed when mclk=256fs/384fs. note 17. the ak5388 can be reset by bringing the pdn pin = ?l?. note 18. this cycle is the number of lrck rising edges from the pdn pin = ?h?. the value is when the ak5388 is in master mode. in case of in slave mode, the va lue will be 1lrck clock cycle (1/fs) longer.
[ak5388] ms1096-e-01 2009/08 - 13 - timing diagram 1/fclk tclkl vih tc lk h mclk vil figure 1. mclk timing (tdm0 pin = ?l? or ?h?) 1/fs lrck vih vil tlrl tlrh figure 2. lrck timing (tdm0 pin = ?l? or ?h?) tbck tbckl vi h tbckh bick vi l duty = tbckh/tbck, tbckl/tbck figure 3.bick timing (tdm0 pin = ?l? or ?h?)
[ak5388] ms1096-e-01 2009/08 - 14 - lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd figure 4. audio interface timing (s lave mode, tdm0 pin = ?l?) note: sdto shows sdto1 and sdto2. tdmin vih vil lrck vih vil tblr bick vih vil sdto1 50%dvdd tlrb tbsd ttdms figure 5. audio interface timing (s lave mode, tdm0 pin = ?h?)
[ak5388] ms1096-e-01 2009/08 - 15 - lrck vih vil tblr bick vih vil sdto1 50%dvdd tlrb tbsd figure 6. audio interface timing (slave mode, tdm0 pin = ?h?, tdm1 pin = ?h?, 8khz fs < 108khz) lrck vih vil tblr bick vih vil tbss sdto1 50%dvdd tlrb tbsh data figure 7. audio interface timing (slave mode, td m0 pin = ?h?, tdm1 pin = ?h?, 108khz < fs 216khz)
[ak5388] ms1096-e-01 2009/08 - 16 - lrck bick 50%dvdd sdto 50%dvdd tbsd tmblr dbck 50%dvdd figure 8. audio interf ace timing (master mode) pdn vih vil tpdv sdto 50%dvdd tpd figure 9. power down & reset timing note: sdto shows sdto1 and sdto2.
[ak5388] ms1096-e-01 2009/08 - 17 - operation overview system clock mclk (128fs/192fs/256fs/384fs/512fs/768fs), bick (48fs ) and lrck (fs) clocks are required in slave mode. the lrck clock input must be sy nchronized with mclk, however the phase is not critical. table 1 , table 2 and table 3 show the relationship of typical sampling frequency and the system clock frequency. mclk frequency is selected by cks1-0 pins as shown in table 4 . since the ak5388 includes a phase detection circuit for lrck, the ak5388 is reset automatically when the synchronization is out of phase af ter changing the clock frequencies. all external clocks (mclk, bick and lrck) must be pr esent unless the pdn pin = ?l?. if these clocks are not provided, the ak5388 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the ak5388 in power-down mode (pdn pin = ?l?). in master mode, the master clock (mclk) must be provided unless the pdn pin = ?l?. in cas e of using two or more devices, the ak5388 should be reset by the pdn pin when changi ng clocks, changing clock mode s and switching digital interf aces for a synchronization. clock or mode changes should be made during the rese t, and a stable clock is needed after the reset. mclk fs 128fs 192fs 256fs 384fs 512fs 768fs 32khz n/a n/a 8.192mhz 12.288mhz 16.384mhz 24.576mhz 48khz n/a n/a 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz n/a n/a 24.576mhz n/a n/a n/a 192khz 24.576mhz 36.864mhz n/a n/a n/a n/a (n/a: not available) table 1. system clock example (slave mode) mclk fs 128fs 192fs 256fs 384fs 512fs 768fs 32khz n/a n/a 8.192mhz 12.288mhz 16.384mhz 24.576mhz 48khz n/a n/a 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz n/a n/a 24.576mhz 36.864mhz n/a n/a 192khz 24.576mhz 36.864mhz n/a n/a n/a n/a (n/a: not available) table 2. system clock example (master mode) mclk fs 128fs 192fs 256fs 384fs 512fs 768fs 32khz n/a n/a n/a n/a 16.384mhz 24.576mhz 48khz n/a n/a n/a n/a 24.576mhz 36.864mhz 96khz n/a n/a 24.576mhz 36.864mhz n/a n/a 192khz 24.576mhz 36.864mhz n/a n/a n/a n/a (n/a: not available) table 3. system clock example (auto mode)
[ak5388] ms1096-e-01 2009/08 - 18 - cks2 pin cks1 pin cks0 pin m/s pin mclk frequency l l l l h double speed mode 128fs (108khz < fs 216khz) l l l h h quad speed mode 192fs (108khz < fs 216khz) l l h l h normal speed mode 256fs (8khz fs 54khz) l l h h h double speed mode 256fs (54khz < fs 108khz) l auto (8khz fs 216khz) h l l h double speed mode 384fs (54khz < fs 108khz) l h l h h normal speed mode 384fs (8khz fs 54khz) l h h l h normal speed mode 512fs (8khz < fs 54khz) h h h l normal speed mode 768fs (8khz fs 54khz) table 4. mclk frequency when changing mclk frequency in master/slave mode , the ak5388 should reset by pdn pin = ?l?. (ex. 12.288mhz(@fs=48khz) at cks1 pin = cks0 pin = ?l?. audio interface format 12 different audio data interface form ats can be selected using the tdm1 -0, m/s and dif pins as shown in table 5 . the audio data format can be selected by the dif pin. in all fo rmats the serial data is msb-first, 2's compliment format. the sdto1/2 is clocked out on the falling edge of bick. in normal mode, mode 0-1 are the slave mode, and bick is available up to 128fs at fs=48khz. bick outputs 64fs clock in mode 2-3. in tdm256 mode, all of the adc?s serial data (four channels) is output from the sdto1 pins. the sdto2 output is fixed to ?l?. bick should be fixed to 256fs. in slave mode, ?h? time and ?l? time of lrck should be at least 1/256fs. in master mode, ?h? time (?l? time at i 2 s mode) of lrck is 1/8fs (typ). tdm256 mode only supports 48khz sampling. in tdm128 mode, all of the adc?s serial data (four channels) is output from the sdto1 pin. the sdto2 output is fixed to ?l?. bick should be fixed to 128fs. in the slave mode, ?h? time and ?l? time of lrck should be at least 1/128fs. in master mode, ?h? time (?l? time at i 2 s mode) of lrck is 1/4fs (typ). tdm128 mode supports up to 192khz sampling.
[ak5388] ms1096-e-01 2009/08 - 19 - lrck bick mode tdm1 tdm0 m/s dif sdto i/o i/o 0 l 24bit, msb justified h/l i 48-128fs i 1 l h 24bit, i 2 s compatible l/h i 48-128fs i 2 l 24bit, msb justified h/l o 64fs o 3 normal l l h h 24bit, i 2 s compatible l/h o 64fs o 4 l 24bit, msb justified i 256fs i 5 l h 24bit, i 2 s compatible i 256fs i 6 l 24bit, msb justified o 256fs o 7 tdm256 l h h h 24bit, i 2 s compatible o 256fs o 8 l 24bit, msb justified i 128fs i 9 l h 24bit, i 2 s compatible i 128fs i 10 l 24bit, msb justified o 128fs o 11 tdm128 h h h h 24bit, i 2 s compatible o 128fs o 12 n/a h l n/a n/a n/a n/a n/a n/a n/a table 5. audio interface form ats (n/a: not available) lrck bick(64fs) sdto1/2(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 lch data rch data 12 11 10 23:msb, 0:lsb figure 10. mode 0/2 timing (normal mode, msb justified) lrck bick(64fs) sdto1/2(o) 0 1 2 3 23 24 25 26 0 0 1 31 29 30 23 22 1 23:msb, 0:lsb lch data rch data 2 0 2 3 23 24 25 26 0 31 29 30 23 22 1 2 0 1 figure 11. mode 1/3 timing (normal mode, i 2 s compatible) 23 lrck (mode 4) bick (256fs) sdto1 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 lrck (mode 6) figure 12. mode 4/6 timing (tdm256 mode, msb justified)
[ak5388] ms1096-e-01 2009/08 - 20 - lrck (mode5) bick (256fs) sdto1 23 0 l1 32 bick 256 bick 23 0 r1 32 bick 23 23 0 l2 32 bick 23 0 r2 32 bick lrck (mode 7) figure 13. mode 5/7 timing (tdm256 mode, i 2 s compatible) lrck (mode 8) bick (128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdto1 22 0 22 0 22 0 22 0 23 23 23 23 22 23 lrck (mode 10) figure 14. mode 8/10 timing (tdm128 mode, msb justified) lrck (mode 9) bick (128fs) 128 bick l1 32 bick r1 32 bick l2 32 bick r2 32 bick sdto1 22 0 22 0 22 0 22 0 23 23 23 23 23 lrck (mode 11) figure 15. mode 9/11 timing (tdm128 mode, i 2 s compatible)
[ak5388] ms1096-e-01 2009/08 - 21 - digital high pass filter (hpf) the adc has a digital high pass filter for dc offset cancellation. the hpf is controlled by the hpfe pin. if the hpf setting (on/off) is changed during operation, a click noise occurs due to the change in dc offset. the hpf setting should only be changed when the pdn pin = ?l?. overflow detection the ak5388 has an overflow detect function for the analog i nput. the ovf pin goes to ?h? if either channel overflows (more than ? 0.3dbfs). ovf output for overflowed analog input has the same group delay as the adc (gd=13/fs=0.27ms@fs=48khz). ovf is ?l? for 516/ fs (=10.75ms@fs=48khz) after the pdn pin = ? ?, and then overflow detection is enabled. power down and reset the ak5388 is placed in the power-down mode by bringing pdn pin ?l? and the digita l filter is also reset at the same time. this reset should always be done after power-up. in the power-down mode, the vcom is agnd level. an analog initialization cycle starts after exiting th e power-down mode. the output data sdto is valid after 516 cycles of lrck clock in master mode (517 cycles in sl ave mode). during initialization, the adc di gital data outputs of both channels are forced to ?0?. the adc outputs settle to data correspondent to the input signals after the end of initialization (settling takes approximately the group delay time). the ak5388 should be reset once by bringing the pdn pin ?l? after power-up. the internal timing starts clocking by the rising edge (falling edge at mode 1) of lrck af ter exiting from reset and power down state by mclk. normal operation internal state pdn power-down initialize normal operation (1) idle noise gd gd ?0?data a /d in (analog) a /d ou t (digital) clock in mclk,lrck,sclk (2) (3) (4) ?0?data idle noise notes: (1) 517/fs in slave mode and 516/fs in master mode. (2) digital output corresponding to analog input has group delay (gd). (3) a/d output is ?0? data in power-down state. (4) when the external clocks (mclk, sclk, lrck) are stopped, the ak5388 should be in the power-down state. figure 16. power-down/up sequence example
[ak5388] ms1096-e-01 2009/08 - 22 - cascade tdm mode the ak5388 supports cascading of up to two devices in a dais y chain configuration in tdm256 mode. in this mode, sdto1 pin of device #1 is connected to tdmin pin of device #2. the sdto1 pin of device #2 can output 8-chnnels of tdm data multiplexed with 4-chnnel of tdm data from device #1 and 4-channel of tdm data from device #2. figure 17 shows a connection example of a daisy chain. when using two ak5388?s in slave mode by cascade connection, the internal timing between device #1 and #2 may differ for 1mclk clock cycle. bick falling edge must me more th an 10ns from a mick rising edge to prevent this phase difference between two devices. ( table 6 ) bick must be divided by two on a mclk falling edge ( figure 19 ) when mclk=2 x bick (normal speed 512fs mode or double speed 256fs mode), and bick must be in-phase signal to mclk ( figure 20 ) when mclk = bick (normal speed 256fs mode or quad speed 128fs mode) to achieve this internal timing synchronization. 48khz 256fs 8ch tdm lrc k a k5388 #1 bic k tdmin sdto1 sdto2 mcl k 256fs or 512fs gnd lrc k a k5388 # 2 bic k tdmin sdto1 sdto2 mcl k figure 17. cascade tdm connection diagram lrck bick(256fs) #1 sdto1(o) 22 0 l1 32 bick 256 bick 22 0 r1 32 bick 22 23 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #1 sdto2(o) 22 0 l1 32 bick 22 0 r1 32 bick 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #2 tdmin(i) 22 0 l1 32 bick 22 0 r1 32 bick 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 #2 sdto1(o) 22 0 l1 32 bick 22 0 r1 32 bick 22 23 23 23 22 0 l2 32 bick 22 0 r2 32 bick 23 23 22 0 l1-#1 32 bick 22 0 r1-#1 32 bick 23 23 22 0 l2-#1 32 bick 22 0 r2-#1 32 bick 23 23 figure 18. cascade tdm timing
[ak5388] ms1096-e-01 2009/08 - 23 - parameter symbol min typ max units mclk ? ? to bick ? ? bick ? ? to mclk? ? tmcb tbim 10 10 ns ns table 6 tdm mode clock timing tbim vi h tmcb mclk vi l vih bick vil figure 19. audio interface timing (slave mode, tdm0 mode mclk=2 x bick) tbim vi h tmcb mclk vi l vih bick vil figure 20. audio interface timing (sla ve mode, tdm0 mode mclk=bick) v mono mode when the mono pin is set to ?h?, the ak5388 is in mono m ode. in this mode, dynamic range and s/n can be improved by approximately 3db when the same analog signal is inputted to lin1 and rin1, lin2 and rin2. the lin1 and rin1 data are summed and the amplitude is attenuated into half to be output from the sdto1 pin. the lin2 and rin2 data are summed and the amplitude is attenuated into half to be output from the sdto2 pin. mono pin sdto1/2 output data l stereo mode h mono mode table 7. setup of mono mode
[ak5388] ms1096-e-01 2009/08 - 24 - system design figure 21 and figure 22 show the system connection diagram. the evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. lin1+ vrefp1 1 lin1- 44 2 vs s1 3 a vdd1 4 test1 5 vs s2 6 cks0 7 cks1 8 cks2 9 pdn 10 m_sn 11 vrefl1 43 vcom1 42 rin1+ 41 rin1 - 40 test3 39 lin2 - 38 lin2+ 37 vcom2 36 vrefl2 35 vr efp2 34 mc lk 12 bick 13 lrck 14 dvdd1 15 vss3 16 sd to1 17 sdto2 18 ovf 19 tdmin 20 tdm0 21 tdm1 22 33 32 31 30 29 28 27 26 25 24 23 rin2+ rin2- vss6 avdd2 test2 vss5 vss4 dvdd2 hpfe mono dif ak5388 top view + digital3.3 v 0.1u 10u + analog5.0v 10u 0.1u 0.1u 10u + 0.1u 2.2u + 10u 0.1u 0.1u + 0.1u + + analog5.0v + 0.1u + digital3.3v 10u 2.2u 10 u ceramic capacitor + electrolytic capacitor lin1+ lin1- rin2+ rin2- lin2+ lin2- rin1+ rin1- micro- controller fs 64fs micro- controller a nalog digital digital note: - vss1-6 should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all digital input pins should not be left floating. figure 21. typical connection diagram
[ak5388] ms1096-e-01 2009/08 - 25 - analog ground digital ground system controller lin 1+ vrefp1 1 lin 1- 44 2 vss1 3 a vdd1 4 test1 5 vss2 6 cks0 7 cks1 8 cks2 9 pdn 10 m/sn 11 mclk 12 33 rin2+ AK5388EQ 13 14 15 16 17 18 19 20 21 22 bi ck lr ck dvdd1 vss3 sdto1 sdto2 ovf tdmin tdm0 tdm1 32 rin2- 31 vss6 30 a vdd2 29 test2 28 vss5 27 vss4 26 dvdd2 25 hpfe 24 mono 23 dif vrefl1 43 vcom1 42 rin1+ 41 rin1- 40 test3 39 li n2- 38 lin2+ 37 vcom 2 36 vrefl2 35 vrefp 2 34 figure 22. ground layout note: vss1-6 must be connected to the same analog ground plane. 1. grounding and power supply decoupling the ak5388 requires careful attention to power suppl y and grounding arrangements. avdd1/2 and dvdd1/2 are usually supplied from the system?s analog supply. alterna tively if avdd1/2 and dvdd1/2 are supplied separately, the power up sequence is not critical. vss1-6 of the ak5388 must be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak5388 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the reference voltage for a/d converter is supplied from vre fp1/2 pins at vrefl1/2 reference. vrefl1/2 pins are connected to analog ground and an electrolytic capacitor over 10 f parallel with a 0.1 f ceramic capacitor between the vrefp1/2 pins and the vrefl1/2 pins eliminate the effects of high frequency noise. it is important that a ceramic capacitor should be as near to the pins as possible. all dig ital signals, especially clocks, should be kept away from the vrefp1/2 pins in order to avoid unwanted coupling into the ak5388. vcom1/2 is a signal ground for this device. an electrolytic capacitor (2.2f typical) attached to the vcom1/2 pins eliminates the effects of high frequency noise. it is important that a ceramic capacitor should be as near to the pins as possible. no load current may be drawn from the vcom1/2 pi ns. all signals, especially clocks, should be kept away from the vcom1/2 pins in order to avoid unwanted coupling into the ak5388. 3. analog inputs the analog input signal is differentially supplied into the modulator via the lin+ (rin+) and the lin ? (rin ? ) pins. the input voltage is the difference between the lin+ (rin+) and lin ? (rin ? ) pins. the full scale signal on each pin is nominally 2.8vpp(typ). the ak5388 can accept input voltages from vss1-6 to avdd1/2. the adc output data format is two?s complement. the internal hpf removes dc offset. the ak5388 samples the analog inputs at 128fs (6.144mhz@fs=48khz, normal speed mode). the digital filter rejects noise above the stop band except for multiples of 128fs. the ak5388 includes an anti-a liasing filter (rc filter) to attenuate a noise around 128fs. the ak5388 requires a +5v analog supply voltage. any vo ltage which exceeds the upper limit of avdd1/2+0.3v and lower limit of vss1-6 ? 0.3v and any current beyond 10ma for the analog input pins (lin+/ ? , rin+/ ? ) should be avoided. excessive currents to the input pins may damage the device. hence input pins must be protected from signals at or beyond these limits. use caution especially when using 15v for other analog circuits in the system.
[ak5388] ms1096-e-01 2009/08 - 26 - 4. external analog circuit examples figure 23 shows an input buffer circuit example 1. (1 st order hpf; fc=0.70hz, 2 nd order lpf; fc=351khz, gain=-14.5db). the analog signal is able to input through xlr or bnc conn ectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xlr input). the input level of this circuit is +/-15.0vpp (ak5388: +/-2.8vpp typ.). when using this circuit, analog characteristics at fs=48khz is dr=120db, s/(n+d)=110db. 4.7k - + - + 91 3.3k 620 - + 91 620 analog in 15.4vpp 68 njm5534 va=+5 vp= 15 4.7k 10 + 10k 10k 0.1 bias va+ 2.9vpp 2.9vpp vp+ vp- bias 1n 3.3k 1n bias 2.2n 68 xlr vin+ vin- jp1 jp2 njm5534 njm5534 a k5388 ain+ a k5388 ain- figure 23.input buffer example1 fin 1hz 10hz frequency response ? 1.77db ? 0.02db table 8. frequency response of hpf fin 20khz 40khz 80khz 6.144mhz frequency response 0.00db 0.00db 0.00db ? 49.68db table 9. frequency response of lpf
[ak5388] ms1096-e-01 2009/08 - 27 - figure 24 shows an input buffer circuit example in mono mode. (1 st order hpf; fc=0.70hz, 2 nd order lpf; fc=351khz, gain=-14.5db). 4.7k - + - + 11 3.3 k 620 - + 11 620 analog in 15 .0vpp 68 njm5534 va =+5 v vp= 15v 4.7k 10 + 11k 10k 0.1 bias va + 2.8vpp 2.8vpp vp+ vp- bi as 1n 3.3 k 1n bias 15n 68 xl r vin+ vin- jp1 jp2 njm5534 njm5534 a k5388 lin+ a k5388 lin- 15n a k5 3 8 8 rin + a k5388 rin- figure 24 external analog circuit examples fin 1hz 10hz frequency response ? 1.77db ? 0.02db table 10. frequency response of hpf fin 20khz 40khz 80khz 6.144mhz frequency response 0.00db 0.00db 0.00db ? 49.68db table 11. frequency response of lpf
[ak5388] ms1096-e-01 2009/08 - 28 - 5. performance plot figure 25 shows a fft measurement result. [conditions] ta=25oc; avdd1/2=5.0v; vrefp1/2=5.0v, vref l1/2=0v, dvdd=3.3v; v ss1=vss2=vss3=vss4=0v; fs=48khz; signal frequency =1khz, -1dbfs, measured by audio precision, system two. -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 25. fft (blue: left channel, red: right channel)
[ak5388] ms1096-e-01 2009/08 - 29 - package 0.10 0.17 material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak5388] ms1096-e-01 2009/08 - 30 - marking a k5388eq xxxxxxx a km 1 1) pin #1 indication 2) audio 4 pro logo 3) date code: xxxxxxx(7 digits) 4) marking code: ak5388 5) akm logo date (yy/mm/dd) revision reason page contents 09/07/09 00 first edition 09/08/xx 01 error correct 1 pin names of block diagram were changed. vrp1 vrefp1, vrl1 vrefl1 vrp2 vrefp2, vrl2 vrefl2 22 cascade tdm mode figure 17 and description were corrected. sdto2 is connected to tdmin sdto1 is connected to tdmin 26 figure 23 a resistor value was corrected. 3.3 3.3k 28 [conditions] vrefl1/2=5.0v =0v revision history
[ak5388] ms1096-e-01 2009/08 - 31 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and a ll responsibility and liability fo r and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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